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STE10/100

Table 3. STE10/100 configuration registers table

Note:

* : automatically recalled from EEPROM when PCI reset is deserted

DS(40h), bit15-8, is read/write able register

SIG(80h) is hard wired register, read only

5.1.1 STE10/100 configuration registers descriptions

offset

b31

-----------

b16

b15

----------

00h

Device ID*

Vendor ID*

04h

Status

Command

08h

Base Class Code

Subclass

------

Revision #

Step #

0ch

------

Latency timer

cache line size

10h

Base I/O address

14h

Base memory address

18h~

28h

Reserved

2ch

Subsystem ID*

Subsystem vendor ID*

30h

Boot ROM base address

34h

Reserved

Cap_Ptr

38h

Reserved

3ch

Max_Lat*

Min_Gnt*

Interrupt pin

Interrupt line

40h

Reserved

Driver Space

Reserved

80h

Signature of STE10/100

c0h

PMC

Next_Item_Ptr

Cap_ID

c4h

Reserved

PMCSR

Table 4. Configuration Registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

CR0(offset = 00h), LID - Loaded Identification number of Device and Vendor

31~16

LDID

Loaded Device ID, the device ID number loaded from serial

EEPROM.

From

EEPROM

R/O

15~0

LVID

Loaded Vendor ID, the vendor ID number loaded from serial

EEPROM.

From

EEPROM

R/O

From EEPROM: Loaded from EEPROM

CR1(offset = 04h), CSC - Configuration command and status

SPE

Status Parity Error.

1: means that STE10/100 detected a parity error. This bit will

be set even if the parity error response (bit 6 of CR1) is

disabled.

R/W

SES

Status System Error.

1: means that STE10/100 asserted the system error pin.

R/W

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