STE10 datasheet(33/66 Pages) STMICROELECTRONICS

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STE10/100

EXT

Extended register support.

Always 1, since STE10/100 supports extended register

1RO

LL* = Latching Low and clear by read. LH* = Latching High and clear by read.

XR2(offset = bch) - PID1, PHY identifier 1

15~0

PHYID1

Part one of PHY Identifier.

Assigned to the 3rd to 18th bits of the Organizationally Unique

Identifier.

0382h

XR3(offset = c0h) - PID2, PHY identifier 2

15~10

PHYID2

Part two of PHY Identifier.

Assigned to the 19th to 24th bits of the Organizationally Unique

Identifier (OUI).

010010b

9~4

MODEL

Model number of STE10/100.

6-bit manufacturer’s model number.

000001b

3~0

REV

Revision number of STE10/100.

4-bits manufacturer’s revision number.

0000b

XR4(offset = c4h) - ANA, Auto-Negotiation Advertisement

NXTPG

Next Page ability.

Always 0; STE10/100 does not provide next page ability.

0RO

---

reserved

Remote Fault function.

1: remote fault function present

R/W

12,11

---

reserved

Flow Control function Ability.

1: supports PAUSE operation of flow control for full duplex link.

R/W

100BASE-T4 Ability.

Always 0; STE10/100 does not provide 100BASE-T4 ability.

0RO

TXF

100BASE-TX Full duplex Ability.

1: 100Base-TX full duplex ability supported

R/W

TXH

100BASE-TX Half duplex Ability.

1: 100Base-TX ability supported.

R/W

10F

10BASE-T Full duplex Ability.

1: 10Base-T full duplex ability supported.

R/W

10H

10BASE-T Half duplex Ability.

1: 10Base-T ability supported.

R/W

4~0

Select field. Default 00001=IEEE 802.3

00001

XR5(offset = c8h) - ANLP, Auto-Negotiation Link Partner ability

LPNP

Link partner Next Page ability.

0: link partner without next page ability.

1: link partner with next page ability.

0RO

Table 8. Transceiver registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

STE10 数据表(PDF) 33 Page - STMicroelectronics

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