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STE10 数据表(PDF) 32 Page - STMicroelectronics

部件名 STE10
功能描述  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
PDF  66 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STE10 数据表(HTML) 32 Page - STMicroelectronics

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STE10/100
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11
PDEN
Power down mode control.
1: transceiver power-down mode is selected. In this mode, the
STE10/100 transceivers are turned off.
0
R/W
10
---
reserved
0
RO
9
RSAN
Re-Start Auto-Negotiation process control.
1: Auto-negotiation process will be restarted. This bit will be
cleared by STE10/100 after the Auto-negotiation has
restarted.
0
R/W
8
DPSEL
Full/Half duplex mode select.
1: full duplex mode is selected. This bit will be ignored if Auto-
Negotiation is enabled (ANEN, XR0 bit 12).
0
R/W
7
COLEN
Collision test control.
1: collision test is enabled.
0
R/W
6~0
---
reserved
0
RO
R/W = Read/Write able. RO = Read Only.
XR1(offset = b8h) - XSR, XCVR Status Register. All the bits of this register are read only.
15
T4
100BASE-T4 ability.
Always 0, since STE10/100 has no T4 ability.
0RO
14
TXFD
100BASE-TX full duplex ability.
Always 1, since STE10/100 has 100BASE-TX full duplex
ability.
1RO
13
TXHD
100BASE-TX half duplex ability.
Always 1, since STE10/100 has 100BASE-TX half duplex
ability.
1RO
12
10FD
10BASE-T full duplex ability.
Always 1, since STE10/100 has 10Base-T full duplex ability.
1RO
11
10HD
10BASE-T half duplex ability.
Always 1, since STE10/100 has 10Base-T half duplex ability.
1RO
10~6
---
reserved
0
RO
5
ANC
Auto-Negotiation Completed.
0: Auto-Negotiation process incomplete.
1: Auto-Negotiation process complete.
0RO
4
RF
Result of remote fault detection.
0: no remote fault condition detected.
1: remote fault condition detected.
0
RO/LH*
3
AN
Auto-Negotiation ability.
Always 1, since STE10/100 has Auto-negotiation ability.
1RO
2
LINK
Link status.
0: a link failure condition occurred. Readin clears this bit.
1: valid link established.
0
RO/LL*
1
JAB
Jabber detection.
1: jabber condition detected (10Base-T only).
0
RO/LH*
Table 8. Transceiver registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type



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