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STE10 数据表(PDF) 21 Page - STMicroelectronics

部件名 STE10
功能描述  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
PDF  66 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STE10 数据表(HTML) 21 Page - STMicroelectronics

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STE10/100
31~17
---
reserved
16
NIE
Normal Interrupt Enable
1: enables all the normal interrupt bits (see bit 16 of CSR5)
0
R/W
15
AIE
Abnormal Interrupt Enable
1: enables all the abnormal interrupt bits (see bit 15 of CSR5)
0
R/W
14
---
reserved
13
FBEIE
Fatal Bus Error Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the fatal bus error interrupt
0
R/W
12
---
Reserved
11
GPTIE
General Purpose Timer Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the general purpose timer expired interrupt.
0
R/W
10
---
Reserved
9
RWTIE
Receive Watchdog Time-out Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive watchdog time-out interrupt.
0
R/W
8
RSIE
Receive Stopped Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive stopped interrupt.
0
R/W
7
RUIE
Receive Descriptor Unavailable Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the receive descriptor unavailable interrupt.
0
R/W
6
RCIE
Receive Completed Interrupt Enable
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the receive completed interrupt.
0
R/W
5
TUIE
Transmit Under-flow Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit under-flow interrupt.
0
R/W
4
---
Reserved
3
TJTTIE
Transmit Jabber Timer Time-out Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit jabber timer time-out interrupt.
0
R/W
2
TDUIE
Transmit Descriptor Unavailable Interrupt Enable
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the transmit descriptor unavailable interrupt.
0
R/W
1
TPSIE
Transmit Processor Stopped Interrupt Enable
1: this bit in conjunction with AIE (bit 15 of CSR7) will enable
the transmit processor stopped interrupt.
0
R/W
0
TCIE
Transmit Completed Interrupt Enable
1: this bit in conjunction with NIE (bit 16 of CSR7) will enable
the transmit completed interrupt.
0
R/W
CSR8(offset = 40h), LPC - Lost packet counter
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type



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