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STE10/100

CRCT

CRC-16 Type

0: Initial contents = 0000h

1: Initial contents = FFFFh

R/W

WP1E

Wake-up Pattern One Matched Enable.

R/W

WP2E

Wake-up Pattern Two Matched Enable.

R/W

WP3E

Wake-up Pattern Three Matched Enable.

R/W

WP4E

Wake-up Pattern Four Matched Enable.

R/W

WP5E

Wake-up Pattern Five Matched Enable.

R/W

24-18

---

Reserved

LinkOFF

Link Off Detect Enable. The STE10/100 will set the LSC bit of

CSR13 after it has detected that link status has transitioned

from ON to OFF.

R/W

LinkON

Link On Detect Enable. The STE10/100 will set the LSC bit of

CSR13 after it has detected that link status has transitioned

from OFF to ON.

R/W

15-11

---

Reserved

WFRE

Wake-up Frame Received Enable. The STE10/100 will

include the “Wake-up Frame Received” event in its set of

wake-up events. If this bit is set, STE10/100 will assert

PMEST bit of PMR1 (CR49) after STE10/100 has received a

matched wake-up frame.

R/W

MPRE

Magic Packet Received Enable. The STE10/100 will include

the “Magic Packet Received” event in its set of wake-up

events. If this bit is set, STE10/100 will assert PMEST bit of

PMR1 (CR49) after STE10/100 has received a Magic packet.

Default 1 if

PM & WOL

bits of CSR

18 are both

enabled.

R/W

LSCE

Link Status Changed Enable. The STE10/100 will include the

“Link Status Changed” event in its set of wake-up events. If

this bit is set, STE10/100 will assert PMEST bit of PMR1 after

STE10/100 has detected a link status changed event.

R/W

7-3

---

Reserved

WFR

Wake-up Frame Received,

1: Indicates STE10/100 has received a wake-up frame. It is

cleared by writing a 1 or upon power-up reset. It is not

affected by a hardware or software reset.

R/W1C*

MPR

Magic Packet Received,

1: Indicates STE10/100 has received a magic packet. It is

cleared by writing a 1 or upon power-up reset. It is not

affected by a hardware or software reset.

R/W1C*

LSC

Link Status Changed,

1: Indicates STE10/100 has detected a link status change

event. It is cleared by writing a 1 or upon power-up reset. It

is not affected by a hardware or software reset.

R/W1C*

R/W1C*, Read Only and Write one cleared.

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

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