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STE10 数据表(PDF) 17 Page - STMicroelectronics |
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STE10 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 66 page ![]() 17/66 STE10/100 0 SWR Software reset 1: reset all internal hardware (including MAC and transceivers), except configuration registers. This signal will be cleared by the STE10/100 itself after the reset process is completed. 0 R/W* R/W* = Before writing the transmit and receive operations should be stopped. CSR1(offset = 08h), TDR - Transmit demand register 31~ 0 TPDM Transmit poll demand. While the STE10/100 is in the suspended state, a write to this register (any value) will trigger the read-tx-descriptor process, which checks the own-bit; if set, the transmit process is then started. FFFFFFFF h R/W* R/W* = Before writing the transmit process should be in the suspended state. CSR2(offset = 10h), RDR - Receive demand register 31 ~ 0 RPDM Receive poll demand While the STE10/100 is in the suspended state, a write to this register (any value) will trigger the read-rx-descriptor process, which checks the own-bit, if set, the process to move data from the FIFO to buffer is then started. FFFFFFFF h R/W* R/W* = Before writing the receive process should be in the suspended state. CSR3(offset = 18h), RDB - Receive descriptor base address 31~ 2 SAR Start address of receive descriptor 0 R/W* 1, 0 RBND must be 00, DW boundary 00 RO R/W* = Before writing the receive process should be stopped. CSR4(offset = 20h), TDB - Transmit descriptor base address 31~ 2 SAT Start address of transmit descriptor 0 R/W* 1, 0 TBND must be 00, DW boundary 00 RO R/W* = Before writing the transmit process should be stopped. CSR5(offset = 28h), SR - Status register 31~ 26 ---- reserved 25~ 23 BET Bus Error Type. This field is valid only when bit 13 of CSR5(fatal bus error) is set. There is no interrupt generated by this field. 000: parity error, 001: master abort, 010: target abort 011, 1xx: reserved 000 RO Table 6. Control/Status register description Bit # Name Descriptions Default Val RW Type |
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