STE10 datasheet(26/66 Pages) STMICROELECTRONICS

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STE10/100

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22~ 20

Transmit State. Reports the current transmission state only,

no interrupt will be generated.

000: stop

001: read descriptor

010: transmitting

011: FIFO fill, read the data from memory and put into FIFO

100: reserved

101: reserved

110: suspended, unavailable transmit descriptor or FIFO

overflow

111: write descriptor

000

19~17

Receive State. Reports current receive state only, no interrupt

will be generated.

000: stop

001: read descriptor

010: check this packet and pre-fetch next descriptor

011: wait for receiving data

100: suspended

101: write descriptor

110: flush the current FIFO

111: FIFO drain, move data from receiving FIFO into memory

000

ANISS

Added normal interrupt status summary.

1: whenever any of the added normal interrupts occur.

RO/LH*

AAISS

Added Abnormal Interrupt Status Summary.

1: whenever any of the added abnormal interrupts occur.

RO/LH*

14~0

These bits are the same as the status register of CSR5, and

are accessible through either CSR5 or CSR16.

LH* = High Latching and cleared by writing 1.

CSR17(offset = 84h), ACSR7- Assistant CSR7(Interrupt enable register 2)

TEIE

Transmit Early Interrupt Enable

R/W

REIE

Receive Early Interrupt Enable

R/W

XIE

Transceiver (XCVR) Interrupt Enable

R/W

TDIE

Transmit Deferred Interrupt Enable

R/W

---

Reserved

PFRIE

PAUSE Frame Received Interrupt Enable

R/W

25~17

---

Reserved

ANISE

Added Normal Interrupt Summary Enable.

1: adds the interrupts of bits 30 and 31 of ACSR7 (CSR17) to

the normal interrupt summary (bit 16 of CSR5).

R/W

AAIE

Added Abnormal Interrupt Summary Enable.

1: adds the interrupt of bits 27, 28, and 29 of ACSR7 (CSR17)

to the abnormal interrupt summary (bit 16 of CSR5).

R/W

14~0

These bits are the same as the interrupt enable register of

CSR7, and are accessible through either CSR7 or CSR16.

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

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