STE10 datasheet(55/66 Pages) STMICROELECTRONICS

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STE10/100

Compatibility with AMD Magic Packet™ Technology.

6.9.1 Power States

DO (Fully On)

In this state the STE10/100 operates with full functionality and consumes normal power. While in the

D0 state, if the PCI clock is lower than 16MHz, the STE10/100 may not receive or transmit frames

properly.

D1, D2, and D3hot

In these states, the STE10/100 doesn’t respond to any accesses except configuration space and full

function context in place. The only network operation the STE10/100 can initiate is a wake-up event.

D3cold (Power Removed)

In this state all function context is lost. When power is restored, a PCI reset must be asserted and the

function will return to D0.

D3hot (Software Visible D3)

When the STE10/100 is brought back to D0 from D3hot the software must perform a full initialization.

The STE10/100 in the D3hot state responds to configuration cycles as long as power and clock are

supplied. This requires the device to perform an internal reset and return to a power-up reset condition

without the RST# pin asserted.

Table 13. Power Stage

Device

State

PCI Bus

State

Function

Context

Clock

Power

Supported

Actions to

Function

Supported

Actions from

Function

Full function context in

place

Full speed

Full

power

Any PCI

transaction

Any PCI

transaction or

interrupt

B0, B1

Configuration

maintained. No Tx and

Rx except wake-up

events

Stopped to

Full speed

PCI configuration

access

Only wake-up

events

B0, B1,

Configuration

maintained. No Tx and

Stopped to

Full speed

PCI configuration

access(B0, B1)

D3hot

B0, B1,

Configuration lost, full

initialization required

upon return to D0

Stopped to

Full speed

PCI configuration

access(B0, B1)

D3cold

All configuration lost.

Power-on defaults in

place on return to D0

No clock

No power

Power-on reset

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