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STE10/100

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

CSR15(offset = 78h), WTMR - Watchdog timer

31~6

---

Reserved

RWR

Receive Watchdog Release. The time (in bit-times) from

sensing dropped carrier to releasing watchdog timer.

0: 24 bit-times

1: 48 bit-times

R/W

RWD

Receive Watchdog Disable

0: If the received packet‘s length exceeds 2560 bytes, the

watchdog timer will expire.

1: disable the receive watchdog.

R/W

---

Reserved

JCLK

Jabber clock

0: cut off transmission after 2.6 ms (100Mbps) or 26 ms

(10Mbps).

1: cut off transmission after 2560 byte-time.

R/W

Non-Jabber

0: if jabber expires, re-enable transmit function after 42 ms

(100Mbps) or 420ms (10Mbps).

1: immediately re-enable the transmit function after jabber

expires.

R/W

JBD

Jabber disable

1: disable transmit jabber function

R/W

CSR16(offset = 80h), ACSR5 - Assistant CSR5(Status register 2)

TEIS

Transmit Early Interrupt status

Transmit early interrupt status is set to 1 when TEIE (bit 31 of

CSR17 set) is enabled and the transmitted packet is moved

from descriptors to the TX-FIFO buffer. This bit is cleared by

writing a 1.

RO/LH*

REIS

Receive Early Interrupt Status.

Receive early interrupt status is set to 1 when REIE (CSR17

bit 30) is enabled and the received packet has filled up its first

receive descriptor. This bit is cleared by writing a 1.

RO/LH*

XIS

Transceiver (XCVR) Interrupt Status. Formed by the logical

OR of XR8 bits 6~0.

RO/LH*

TDIS

Transmit Deferred Interrupt Status.

RO/LH*

---

Reserved

PFR

PAUSE Frame Received Interrupt Status

1: indicates receipt of a PAUSE frame while the PAUSE

function is enabled.

RO/LH*

25~ 23

BET

Bus Error Type. This field is valid only when FBE (CSR5 bit

13, fatal bus error) is set. There is no interrupt generated by

this field.

000: parity error, 001: master abort, 010: target abort

011, 1xx: reserved

000

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