STE10 datasheet(13/66 Pages) STMICROELECTRONICS

13 / 66 page

13/66

STE10/100

15~8

Driver Space for implementation-specific purpose. Since this

area won’t be cleared upon software reset, an STE10/100

driver can use this R/W area as user-specified storage.

R/W

7 ~ 0

---

reserved

CR32(offset = 80h), SIG - Signature of STE10/100

31~16

DID

Device ID, the device ID number of the STE10/100.

0981h

15~0

VID

Vendor ID

1317h

CR48(offset = c0h), PMR0, Power Management Register0.

PSD3c,

PSD3h,

PSD2,

PSD1,

PSD0

PME_Support.

The STE10/100 will assert PME# signal while in the D0, D1,

D2, D3hot and D3cold power state. The STE10/100 supports

Wake-up from the above five states. Bit 31 (support wake-up

from D3cold) is loaded from EEPROM after power-up or

hardware reset. To support the D3cold wake-up function, an

auxiliary power source will be sensed during reset by the

STE10/100 Vaux_detect pin. If sensed low, PSD3c will be set

to 0; if sensed high, and if D3CS (bit 31of CSR18) is set

(CSR18 bits 16~31 are recalled from EEPROM at reset), then

bit 31 will be set to 1.

X1111b

D2S

D2_Support. The STE10/100 supports the D2 Power

Management State.

1RO

D1S

D1_Support. The STE10/100 supports the D1 Power

Management State.

1RO

24~22

AUXC

Aux Current. These three bits report the maximum 3.3Vaux

current requirements for STE10/100 chip. If bit 31 of PMR0 is

‘1’, the default value is 111b, meaning the STE10/100 needs

375 mA to support remote wake-up in D3cold power state.

Otherwise, the default value is 000b, meaning the STE10/100

does not support remote wake-up from D3cold power state.

XXXb

DSI

The Device Specific Initialization bit indicates whether any

special initialization of this function is required before the

generic class device driver is able to use it.

0: indicates that the function does not require a device-specific

initialization sequence following transition to the D0

uninitialized state.

0RO

---

Reserved.

PMEC

PME Clock. Indicates that the STE10/100 does not rely on the

presence of the PCI clock for PME# operation

0RO

18~16

VER

Version. The value of 010b indicates that the STE10/100

complies with Revision 1.0a of the PCI Power Management

Interface Specification.

010b

15~8

NIP

Next Item Pointer. This value is always 0h, indicating that

there are no additional items in the Capabilities List.

00h

7~0

CAPID

Capability Identifier. This value is always 01h, indicating the

link list item as being the PCI Power Management Registers.

01h

Table 4. Configuration Registers Descriptions

Bit #

Name

Descriptions

Default Val

RW Type

STE10 数据表(PDF) 13 Page - STMicroelectronics

STE10 数据表(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载