STE10 datasheet(39/66 Pages) STMICROELECTRONICS

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STE10/100

5.4.2 Transmit Descriptor

Table 11. Transmit Descriptor Table

Note: 1. Descriptor addresses must be longword alignment

RCH

Second address chain

Used for chain structure, indicating the buffer 2 address is the next descriptor address. Ring

mode takes precedence over chained mode

23~22

---

reserved

21~11

RBS2

Buffer 2 size (DW boundary)

10~ 0

RBS1

Buffer 1 size (DW boundary)

RDES2

31~0

RBA1

Receive Buffer Address 1. This buffer address should be double word aligned.

RDES3

31~0

RBA2

Receive Buffer Address 2. This buffer address should be double word aligned.

TDES0

Own

Status

TDES1

Control

Buffer2 byte-count

Buffer1 byte-count

TDSE2

Buffer1 address

TDSE3

Buffer2 address

Table 12. Transmit Descriptor Descriptions

Bit#

Name

Descriptions

TDSE0

OWN

Own bit

1: Indicates this descriptor is ready to transmit

0: No transmit data in this descriptor.

30-24

---

Reserved

23-22

Under-run count

21-16

---

Reserved

Error summary. Logical OR of the following bits:

1: under-run error

8: excessive collision

9: late collision

10: no carrier

11: loss carrier

14: jabber time-out

Transmit jabber time-out

Table 10. Receive Descriptor Descriptions

Bit#

Name

Descriptions

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