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STE10/100

4.0 4. PIN DESCRIPTION

Table 1. Pin Description

Pin No.

Name

Type

Description

PCI bus Interface

113

INTA#

O/D

PCI interrupt request. STE10/100 asserts this signal when one of the interrupt

event is set.

114

RST#

PCI Reset signal to initialize the STE10/100. The RST signal should be asserted

for at least 100

µs to ensure that the STE10/100 completes initialization. During

the reset period, all the output pins of STE10/100 will be placed in a high-

impedance state and all the O/D pins are floated.

116

PCI-CLK

PCI clock input to STE10/100 for PCI Bus functions. The Bus signals are

synchronized relative to the rising edge of PCI-CLK PCI-CLK must operate at a

frequency in the range between 20MHz and 33MHz to ensure proper network

operation

117

GNT#

PCI Bus Granted. This signal indicates that the STE10/100 has been granted

ownership of the PCI Bus as a result of a Bus Request.

118

REQ#

PCI Bus Request. STE10/100 asserts this line when it needs access to the PCI

Bus.

119

PME#

The Power Management Event signal is an open drain, active low signal. The

STE10/100 will assert PME# to indicate that a power management event has

occurred.

When WOL (bit 18 of CSR18) is set, the STE10/100 is placed in Wake On LAN

mode. While in this mode, the STE10/100 will activate the PME# signal upon

receipt of a Magic Packet frame from the network.

In the Wake On LAN mode, when LWS (bit 17 of CSR18) is set, the LAN-WAKE

signal follows HP’s protocol; otherwise, it is IBM protocol.

120,121

123,124

126,127

1,2

6,7

9,10

12,13

15,16

29,30

32~35

43,44

46,47

49,50

52,53

AD-31,30

AD-29,28

AD-27,26

AD-25,24

AD-23,22

AD-21,20

AD-19,18

AD-17,16

AD-15,14

AD-13~10

AD-9

AD-8

AD-7, 6

AD-5,4

AD-3,2

AD-1,0

I/O

Multiplexed PCI Bus address/data pins

C-BEB3

C-BEB2

C-BEB1

C-BEB0

I/O

Bus command and byte enable

IDSEL

Initialization Device Select. This signal is asserted when the host issues

configuration cycles to the STE10/100.

FRAME#

I/O

Asserted by PCI Bus master during bus tenure

IRDY#

I/O

Master device is ready to begin data transaction

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