STE10 datasheet(29/66 Pages) STMICROELECTRONICS

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STE10/100

PME_En

PME_En. When set, enables the STE10/100 to assert PME#.

When cleared, disables the PME# assertion.

0RO

7~2

---

reserved.

000000b

1,0

PWRS

PowerState, This two-bit field is used both to determine the

current power state of the STE10/100 and to set the STE10/

100 into a new power state. The definition of this field is given

below.

00b - D0

01b - D1

10b - D2

11b - D3hot

If software attempts to write an unsupported state to this field,

the write operation will complete normally on the bus, but the

data is discarded and no state change occurs.

00b

CSR23(offset = 9ch) - TXBR, transmit burst count / time-out

31~21

---

reserved

20~16

TBCNT

Transmit Burst Count

Specifies the number of consecutive successful transmit burst

writes to complete before the transmit completed interrupt will

be generated.

R/W

11~0

TTO

Transmit Time-Out = (deferred time + back-off time).

When TDIE (ACSR7 bit 28) is set, the timer is decreased in

increments of 2.56us (@100M) or 25.6us (@10M). If the timer

expires before another packet transmit begins, then the TDIE

interrupt will be generated.

R/W

CSR24(offset = a0h) - FROM, Flash ROM(also the boot ROM) port

bra16_on

This bit is only valid when 4 LEDmode_on (CSR18 bit 23) is

set. In this case, when bra16_on is set, pin 87 functions as

brA16; otherwise it functions as LED pin – fd/col.

R/W

30~28

---

reserved

REN

Read Enable. Clear if read data is ready in DATA, bit7-0 of

FROM.

R/W

WEN

Write Enable. Cleared if write completed.

R/W

---

reserved

24~8

ADDR

Flash ROM address

R/W

7~0

DATA

Read/Write data of flash ROM

R/W

CSR25(offset = a4h) - PAR0, physical address register 0, automatically recalled from EEPROM

31~24

PAB3

physical address byte 3

From

EEPROM

R/W

23~16

PAB2

physical address byte 2

From

EEPROM

R/W

15~8

PAB1

physical address byte 1

From

EEPROM

R/W

Table 6. Control/Status register description

Bit #

Name

Descriptions

Default Val

RW Type

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