R8CSLASH2G datasheet(106/344 Pages) RENESAS

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R8C/2G Group

10. Bus

Rev.1.00

Apr 04, 2008

Page 86 of 318

REJ09B0387-0100

10. Bus

The bus cycles differ when accessing ROM/RAM, and when accessing SFR.

Table 10.1 lists Bus Cycles by Access Space of the R8C/2G Group.

ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are

accessed twice in 8-bit units.

Table 10.2 lists Access Units and Bus Operations.

Table 10.2

Access Units and Bus Operations

Table 10.1

Bus Cycles by Access Space of the R8C/2G Group

Access Area

Bus Cycle

SFR

2 cycles of CPU clock

ROM/RAM

1 cycle of CPU clock

Area

SFR

Even address

Byte access

ROM, RAM

Odd address

Byte access

Even address

Word access

Odd address

Word access

CPU clock

Data

Even

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

CPU

clock

Data

Address

Data

Odd

Data

Even

Even + 1

Data

Odd

Odd + 1

Data

Even

Even + 1

Data

Odd

Odd + 1

Data

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