R8CSLASH2G datasheet(109/344 Pages) RENESAS

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R8C/2G Group

11. Clock Generation Circuit

Rev.1.00

Apr 04, 2008

Page 89 of 318

REJ09B0387-0100

Figure 11.2

CM0 Register

System Clock Control Register 0(1)

Symbol

Address

After Reset

CM0

0006h

01011000b

Bit Symbol

Bit Name

Function

NOTES:

5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

—

(b1)

Reserved bit

Set to 0.

CM03

XCIN-XCOUT drive capacity

select bit(2)

0 : LOW

1 : HIGH

CM04

b7 b6 b5 b4 b3 b2 b1 b0

—

(b0)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CM02

WAIT peripheral function clock

stop bit

0 : Peripheral function clock does not stop

in w ait mode

1 : Peripheral function clock stops in w ait

mode

Port, XCIN-XCOUT sw itch bit(3, 4) 0 : Ports P4_3, P4_4

1 : XCIN-XCOUT pin

—

(b5)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CM06

System clock division select bit

0(5)

0 : CM16, CM17 enabled

1 : Divide-by-8 mode

—

(b7)

Reserved bit

Set to 0.

P4_3 and P4_4 can be used as ports w hen the CM04 bit is set to 0 (ports P4_3 and P4_4).

To use the XCIN clock, set the CM04 bit to 1 (XCIN-XCOUT pin). Also, set port P4_3 as input port w ithout pull-up.

Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.

When entering stop mode, the CM03 bit is set to 1 (HIGH). Rew rite the CM03 bit w hile the XCIN clock oscillation

stabilizes.

If the CM10 bit in the CM1 register is set to 1 (stop mode), w hen the CM04 bit is set to 1 (XCIN-XCOUT pin), the

XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to

0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is

entered).

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