R8CSLASH2G datasheet(113/344 Pages) RENESAS

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R8C/2G Group

11. Clock Generation Circuit

Rev.1.00

Apr 04, 2008

Page 93 of 318

REJ09B0387-0100

Figure 11.6

CPSRF Register

Figure 11.7

Registers FRA4 and FRA6

Clock Prescaler Reset Flag

Symbol

Address

After Reset

CPSRF

0028h

00h

Bit Symbol

Bit Name

Function

NOTE:

1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .

CPSR

Clock prescaler reset flag(1)

Setting this bit to 1 initializes the clock

prescaler. (When read, the content is 0)

—

(b6-b0)

Reserved bits

Set to 0.

0000

000

b3 b2 b1 b0

b7 b6 b5 b4

High-Speed On-Chip Oscillator Control Register 4

Symbol

Address

After Reset

FRA4

0029h

When Shipping

Function

Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that

of the HRA1 register after a reset.) Optimal frequency correction to match the voltage

conditions can be achieved by transferring this value to the HRA1 register.

b3 b2 b1 b0

b7 b6 b5 b4

High-Speed On-Chip Oscillator Control Register 6

Symbol

Address

After Reset

FRA6

002Bh

When Shipping

Function

Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction

to match the voltage conditions can be achieved by transferring this value to the HRA1

b3 b2 b1 b0

b7 b6 b5 b4

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