R8CSLASH2G datasheet(110/344 Pages) RENESAS

110 / 344 page

R8C/2G Group

11. Clock Generation Circuit

Rev.1.00

Apr 04, 2008

Page 90 of 318

REJ09B0387-0100

Figure 11.3

CM1 Register

System Clock Control Register 1(1)

Symbol

Address

After Reset

CM1

0007h

00h

Bit Symbol

Bit Name

Function

NOTES:

Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.

b7 b6 b5 b4 b3 b2 b1 b0

—

(b1)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CM10

All clock stop control bit(2, 3, 4)

0 : Clock operates

1 : Stops all clocks (stop mode)

—

(b3)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CM12

XCIN-XCOUT on-chip feedback

resistor select bit

0 : On-chip feedback resistor enabled

1 : On-chip feedback resistor disabled

—

(b5)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

CM14

Low -speed on-chip oscillation stop

bit(4, 5, 6, 7)

0 : Low -speed on-chip oscillator on

1 : Low -speed on-chip oscillator off

CM17

b7 b6

0 0 : No division mode

0 1 : Divide-by-2 mode

1 0 : Divide-by-4 mode

1 1 : Divide-by-16 mode

System clock division select bits 1(8)

CM16

When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14

bit to 0 (low -speed on-chip oscillator on).

In count source protect mode enabled, the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains

unchanged even if 1 is w ritten to it.

When the CM06 bit in the CM0 register is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.

If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.

If the CM10 bit is set to 1 (stop mode), w hen the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin), the

XCIN(P4_3) pin is set to the high-impedance state and the XCOUT (P4_4) pin is set to “H”. When the CM04 bit is set to

0 (I/O ports P4_3 and P4_4), pins XCIN (P4_3) and XOUT (P4_4) retain the I/O status (status just before stop mode is

entered).

In count source protect mode enabled of w atchdog timer (refer to 16.2 Count Source Protection Mode

Enabled), the value remains unchanged even if bits CM10 and CM14 are set.

When the OCD2 bit in the OCD register is set to 0 (XCIN clock selected), the CM14 bit is set to 1 (low -speed on-chip

oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed

on-chip oscillator on). It remains unchanged even if 1 is w ritten to it.

R8C/2G 数据表(PDF) 110 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 110 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

R8C/2G 数据表(PDF) 110 Page - Renesas Technology Corp

R8C/2G 数据表(HTML) 110 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载