R8CSLASH2G datasheet(122/344 Pages) RENESAS

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R8C/2G Group

11. Clock Generation Circuit

Rev.1.00

Apr 04, 2008

Page 102 of 318

REJ09B0387-0100

Figure 11.11 shows the Time from Wait Mode to Interrupt Routine Execution.

When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT

instruction.

(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral

function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function

interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).

(2) Set the I flag to 1.

(3) Operate the peripheral function to be used for exiting wait mode.

When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request

generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,

as described in Figure 11.11.

The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock

when the WAIT instruction is executed.

Figure 11.11

Time from Wait Mode to Interrupt Routine Execution

Wait mode

Flash memory

activation sequence

CPU clock restart sequence

Interrupt sequence

Interrupt request generated

Time for Interrupt

Sequence (T3)

Remarks

Time until Flash Memory

is Activated (T1)

Time until CPU Clock

is Supplied (T2)

Period of CPU clock

× 20 cycles

Same as above

Following total

time is the time

from wait mode

until an interrupt

routine is

executed.

Period of system clock

× 12 cycles + 30 µs (max.)

Period of system clock

× 12 cycles

Period of CPU clock

× 6 cycles

Same as above

FMSTP Bit

FMR0 Register

(flash memory operates)

(flash memory stops)

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