R8CSLASH2G datasheet(126/344 Pages) RENESAS

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R8C/2G Group

11. Clock Generation Circuit

Rev.1.00

Apr 04, 2008

Page 106 of 318

REJ09B0387-0100

11.5

Notes on Clock Generation Circuit

11.5.1

Stop Mode

When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the

CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction

which sets the CM10 bit to 1 (stop mode) and the program stops.

Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit

to 1.

• Program example to enter stop mode

BCLR

1,FMR0

; CPU rewrite mode disabled

BSET

0,PRCR

; Protect disabled

FSET

; Enable interrupt

BSET

0,CM1

; Stop mode

JMP.B

LABEL_001

LABEL_001 :

NOP

11.5.2

Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and

execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the

program stops. Insert at least 4 NOP instructions after the WAIT instruction.

• Program example to execute the WAIT instruction

BCLR

1,FMR0

; CPU rewrite mode disabled

FSET

; Enable interrupt

WAIT

; Wait mode

NOP

11.5.3

Oscillation Circuit Constants

Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.

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