R8CSLASH2G datasheet(215/344 Pages) RENESAS

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R8C/2G Group

17. Timers

Rev.1.00

Apr 04, 2008

Page 195 of 318

REJ09B0387-0100

Figure 17.42

TRECSR Register in Output Compare Mode

Timer RE Count Source Select Register

Symbol

Address

After Reset

TRECSR

011Eh

00001000b

Bit Symbol

Bit Name

Function

NOTES:

Clock output select bits(2)

b6 b5 b4

0 0 0 : f2

0 0 1 : fC

0 1 0 : f4

1 0 0 : f8

1 1 0 : Compare output

Other than above : Do not set.

Write to bits RCS0 to RCS1 w hen the TCSTF bit in the TRECR1 register is set to 0 (count stopped).

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

RCS6

RCS5

RCS4

4-bit counter select bit

0 : Not used

1 : Used

Write to bits RCS4 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).

RCS2

—

(b7)

—

Real-time clock mode select bit

Set to 0 in output compare mode.

RCS1

Count source select bits(1)

b1 b0

0 0 : f4

0 1 : f8

1 0 : f32

1 1 : fC4

b7 b6 b5 b4 b3 b2

RCS3

b1 b0

RCS0

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