R8CSLASH2G datasheet(272/344 Pages) RENESAS

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R8C/2G Group

20. Flash Memory

Rev.1.00

Apr 04, 2008

Page 252 of 318

REJ09B0387-0100

20.4.1.2

FMR1 Register (FMR1)

Figure 20.4 shows the FMR1 Register.

Figure 20.4

FMR1 Register

• FMR11 Bit

Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.

• FMR15 Bit

When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0

accepts program and block erase commands.

• FMR16 Bit

When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1

accepts program and block erase commands.

Flash Memory Control Register 1

Symbol

Address

After Reset

FMR1

01B5h

1000000Xb

Bit Symbol

Bit Name

Function

NOTES:

b3 b2

Set to 0.

b1 b0

FMR11

—

(b4-b2)

b7 b6 b5 b4

FMR15

—

(b0)

Reserved bits

When read, the content is undefined.

EW1 mode select bit(1, 2)

0 : EW0 mode

1 : EW1 mode

Block 0 rew rite disable bit(2,3)

0 : Enables rew rite

1 : Disables rew rite

While the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.

To set this bit to 0, set it to 0 immediately after setting it first to 1.

To set this bit to 1, set it to 1.

—

(b7)

Reserved bit

0 : Enables rew rite

1 : Disables rew rite

FMR16

Block 1 rew rite disable bit(2,3)

To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode

enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.

This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled).

Reserved bit

Set to 1.

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