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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8S/2218 数据表(PDF) 207 Page - Renesas Technology Corp |
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H8S/2218 数据表(HTML) 207 Page - Renesas Technology Corp |
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207 / 750 page  Section 7 DMA Controller (DMAC) Rev.6.00 Jun. 03, 2008 Page 159 of 698 REJ09B0074-0600 7.2 Register Configuration The DMAC registers are listed below. • Memory address register 0A (MAR0A) • I/O address register 0A (IOAR0A) • Transfer count register 0A (ETCR0A) • Memory address register 0B (MAR0B) • I/O address register 0B (IOAR0B) • Transfer count register 0B (ETCR0B) • Memory address register 1A (MAR1A) • I/O address register 1A (IOAR1A) • Transfer count register 1A (ETCR1A) • Memory address register 1B (MAR1B) • I/O address register 1B (IOAR1B) • Transfer count register 1B (ETCR1B) • DMA control register 0A (DMACR0A) • DMA control register 0B (DMACR0B) • DMA control register 1A (DMACR1A) • DMA control register 1B (DMACR1B) • DMA band control register (DMABCR) The DMAC register functions differs depending on the address modes: short address mode and full address mode. The DMAC register functions are described in each address mode. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. |
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