H8SSLASH2218 datasheet(209/750 Pages) RENESAS

209 / 750 page

Section 7 DMA Controller (DMAC)

Rev.6.00 Jun. 03, 2008 Page 161 of 698

REJ09B0074-0600

7.3

7.3.1

Memory Address Registers (MAR)

• Short Address Mode

MAR is a 32-bit readable/writable register that specifies the transfer source address or

destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and

cannot be modified. Whether MAR functions as the source address register or as the

destination address register can be selected by means of the DTDIR bit in DMACR.

MAR is incremented or decremented each time a byte or word transfer is executed, so that the

address specified by MAR is constantly updated. For details, see section 7.3.4, DMA Control

• Full Address Mode

MAR is a 32-bit readable/writable register; MARA functions as the transfer source address

MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are

reserved: they are always read as 0, and cannot be modified. MAR is incremented or

decremented each time a byte or word transfer is executed, so that the source or destination

memory address can be updated automatically. For details, see section 7.3.4, DMA Control

7.3.2

I/O Address Register (IOAR)

• Short Address Mode

IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer

source address or destination address. The upper 8 bits of the transfer address are automatically

set to H'FF. Whether IOAR functions as the source address register or as the destination

address register can be selected by means of the DTDIR bit in DMACR.

IOAR is not incremented or decremented each time a transfer is executed, so that the address

specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode.

• Full Address Mode:

IOAR is not used in full address mode transfer.

H8S/2218 数据表(PDF) 209 Page - Renesas Technology Corp