CS42324 datasheet(50/71 Pages) CIRRUS

50 / 71 page

DS721A6

CS42324

6.5

Serial Port 2 Control (Address 04h)

6.5.1

Serial Port 2 Master/Slave Select

This bit configures Serial Port 2 to operate as either a clock master or clock slave.

6.5.2

Serial Port 2 Speed Mode

In Master Mode this bit configures the speed mode of Serial Port 2.

6.5.3

MCLK2 Divider

These bits configure the internal MCLK2 dividers.

6.5.4

Serial Port 2 MCLK Source

This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 2.

6.6

ADC Clocking (Address 06h)

6.6.1

ADC MCLK Source

This bit selects which MCLK pin provides the clock for the ADC.

543

SP2_M/S

Reserved

Reserved0

SP2_SPEED

MCLK2

FREQ1

MCLK2

FREQ0

Reserved

SP2_MCLK

SP2_M/S

Serial Port 2 Master/Slave Select

Slave Mode

Master Mode

SP2_SPEED

Serial Port 2 Speed Mode

Single-Speed Mode (SSM)

Double-Speed Mode (DSM)

MCLK2

FREQ[1:0]

MCLK Divider

÷1

÷1.5

÷2

÷3

SP2_MCLK

Serial Port 2 MCLK source

MCLK1

1MCLK2

543

Reserved

ADC_MCLK

Reserved

ADC_SP

Reserved

ADC_DIF1

ADC_DIF0

ADC_MCLK

ADC MCLK source

MCLK1

1MCLK2

CS42324 数据表(PDF) 50 Page - Cirrus Logic

CS42324 数据表(HTML) 50 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表下载

链接网址

CS42324 数据表(PDF) 50 Page - Cirrus Logic

CS42324 数据表(HTML) 50 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表 下载

链接网址

数据表下载