| 数据搜索系统,热门电子元器件搜索 |
|
CS42324 数据表(PDF) 28 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS42324 数据表(HTML) 28 Page - Cirrus Logic |
|
28 / 71 page ![]() 28 DS721A6 CS42324 4. APPLICATIONS 4.1 System Clocking The CS42324 will operate at sampling frequencies from 4 kHz to 108 kHz. This range is divided into two speed modes as shown in Table 2. The CS42324 has two serial ports which can operate synchronously or asynchronously. Serial Port 1 (SP1) consists of the SCLK1 and LRCK1 signals. Serial Port 2 (SP2) consists of the SCLK2 and LRCK2 signals. The serial audio output, SDOUT, and serial audio inputs, SDIN1 and SDIN2, can be independent- ly assigned to either of the two serial ports for ease of clocking. Each serial port may be independently placed into Single- or Double-Speed Mode. The serial ports may also be independently placed into Master or Slave Mode. 4.1.1 Master Clock In both Synchronous and Asynchronous Modes, MCLKx (MCLK1 and/or MCLK2) and the corresponding LRCKx must maintain an integer ratio. Some common ratios are shown in Tables 3 and 4. The LRCKx frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SP1_SPEED and SP2_SPEED bits and the MCLKx FREQ bits configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode when auto detect mode is disabled. Tables 3 and 4 illustrate several standard audio sample rates and the required MCLKx and LRCKx frequencies. Speed Mode Master Mode Sampling Frequency Slave Mode Sampling Frequency Single-Speed 4-54 kHz 4-54 kHz Double-Speed 50-108 kHz 50-108 kHz Table 2. Speed Modes Mode LRCKx (kHz) MCLKx (MHz) 128x 192x 256x 384x 512x 768x SINGLE SPEED MODE (SSM) 32 - - 8.1920 12.2880 16.3840 24.5760 44.1 - - 11.2896 16.9344 22.5792 33.8680 48 - - 12.2880 18.4320 24.5760 36.8640 MCLKx FREQ [1:0] - - 000110 11 MDIV pin - - 0 - 1 - Table 3. Single-Speed Mode Common Clock Frequencies Mode LRCKx (kHz) MCLKx (MHz) 128x 192x 256x 384x 512x 768x DOUBLE SPEED MODE (DSM) 64 8.1920 12.2880 16.3840 24.5760 - - 88.2 11.2896 16.9344 22.5792 33.8680 - - 96 12.2880 18.4320 24.5760 36.8640 - - MCLKx FREQ [1:0] 000110 11 - - MDIV pin 0 - 1 - - - Table 4. Double-Speed Mode Common Clock Frequencies |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |