CS42324 datasheet(39/71 Pages) CIRRUS

39 / 71 page

DS721A6

CS42324

4.5.4

Initialization Flow Chart

Figure 19. Initialization Flow Chart

DAC / ADC

Initialization

Software Mode

Registers setup to

desired settings.

RST = Low?

No Power

1. No audio signal

generated.

Off Mode (Power Applied)

1. No audio signal generated.

2. Control Port Registers reset

to default.

Pull-up on SDOUT?

Hardware Mode

Minimal feature

set support.

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCKx valid.

2. SCLKx valid.

3. Audio samples

processed.

Valid

MCLKx/LRCKx

Ratio?

Yes

Normal Operation

Audio signal generated per control port or stand-

alone settings.

Analog Output Freeze

1. AOUTx bias = last audio sample.

2. DAC Modulators stop operation.

3. Audible pops.

ERROR: MCLKx removed

PDN bit set to '1'b

(software mode only)

Standby Mode

1. No audio signal generated.

2. Control Port Registers retain

settings.

3. Update Control Port Registers

as Required.

Reset Transition

1. Pops suppressed.

Power Off Transition

1. Audible pops.

ERROR: Power removed

20 ms delay

Charge Caps

1. VCMADC/VCMDAC

Charged to quiescent voltage.

2. Filt+/VBIAS Charged.

2048 internal

MCLKx cycle delay

Digital/Analog

Output Muted

μs delay (DAC

only)

Stand-By

Transition

1. Pops suppressed.

ERROR: MCLKx/LRCKx ratio change

RST = Low

Power Applied

CS42324 数据表(PDF) 39 Page - Cirrus Logic

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