CS42324 datasheet(10/71 Pages) CIRRUS

10 / 71 page

DS721A6

CS42324

1.2

Hardware Mode

Pin Name

Pin Description

M0, M1

1, 2

Mode Selection (Input) - Determines the operational mode of the device.

MDIV

MCLK Divider (Input) - Setting this pin high places a divide-by-2 circuit in the MCLK path to the

core device circuitry.

MUTE

MUTE (Input) - Engages the internal digital mute and activates the MUTECx pins

DIF

DIF (Input) - Sets the serial audio interface format. Setting DIF high selects I²S audio format and

low selects LJ audio format.

FILT+

FILT+ (Output) - Full-scale reference voltage for ADC.

VCMADC

ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent refer-

ence voltage.

GND

Analog Ground (Input) - Analog ground reference.

Analog Power (Input) - Positive power for the internal analog section.

VBIAS

Bias Voltage (Output) - Positive reference voltage for the internal DAC.

MUTEC1

Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the

clicks and pops associated with any single-rail output. This pin will become a high-impedance out-

put during power-down mode or when an invalid MCLK to LRCK ratio is detected.

MUTEC2

Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the

clicks and pops associated with any single-rail output. This pin will become a high-impedance out-

put during power-down mode or when an invalid MCLK to LRCK ratio is detected.

OVFL

RST

AIN1A

AIN1B

AIN2A

AIN2B

AIN3A

AIN3B

AIN4A

AIN4B

AIN5A

AIN5B

MDIV

MUTE

DIF

FILT+

VCMADC

GND

VBIAS

MUTEC1

MUTEC2

CS42324

CS42324 数据表(PDF) 10 Page - Cirrus Logic

CS42324 数据表(HTML) 10 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表下载