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CS42324 数据表(PDF) 43 Page - Cirrus Logic |
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CS42324 数据表(HTML) 43 Page - Cirrus Logic |
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43 / 71 page ![]() DS721A6 43 CS42324 5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring CS high, and follow the procedure detailed from step 1. If no further reads from other registers are desired, bring CS high. 4.6.4 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.6.4.1 Map Increment (INCR) The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. 4.7 Interrupts and Overflow The CS42324 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active low open-drain driver (see “Operational Control (Address 02h)” on page 47). When configured as ac- tive low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook- ups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for proper operation. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Interrupt Status (Address 18h) (Read Only)” on page 61. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are pos- sible, depending on the needs of the equipment designer. Reading the Interrupt Status register will clear the interrupt condtion. The CS42324 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADC Overflow Positive and Negative conditions available in the Interrupt Status register; however, these conditions do not need to be unmasked for proper operation of the OVFL pin. MA P MSB LSB DATA by te 1 by te n R/W R/W AD D R ES S CH IP ADDRESS CH I P MSB LSB MSB LSB MAP = Memory Address Pointer, 8 bits, MSB first High Impedance 1001111 1001111 CCLK CDIN CDOUT CS Figure 22. Software Mode Timing, SPI Mode |
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