CS42324 datasheet(64/71 Pages) CIRRUS

64 / 71 page

DS721A6

CS42324

7. GROUNDING AND POWER SUPPLY DECOUPLING

As with any high-resolution converter, the CS42324 requires careful attention to power supply and grounding ar-

rangements if its potential performance is to be realized. Figure 7 on page 26 shows the recommended power ar-

rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system

logic supply (VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices

should be powered from VD.

Power supply decoupling capacitors should be as near to the CS42324 as possible, with the low value ceramic ca-

pacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+, VCM_ADC, VBIAS,

VCMBUF, and VCMDAC pins in order to avoid unwanted coupling into the modulators. The FILT+, VCM_ADC,

VBIAS, VCMBUF, and VCMDAC decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the

electrical path from each pin to GND. The CS42324 evaluation board demonstrates the optimum layout and power

supply arrangements. To minimize digital noise, connect the CS42324 digital outputs only to CMOS inputs.

CS42324 数据表(PDF) 64 Page - Cirrus Logic