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CS42324 数据表(PDF) 22 Page - Cirrus Logic

部件名 CS42324
功能描述  10-In, 6-Out, 2 Vrms Audio CODEC
PDF  71 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42324 数据表(HTML) 22 Page - Cirrus Logic

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22
DS721A6
CS42324
SWITCHING CHARACTERISTICS - SERIAL AUDIO
Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VL; CL = 20 pF.
Notes: 17. Duty cycle of generated SCLKx in Master Mode depends on duty cycle of the corresponding MCLKx as
specified under “System Clocking” on page 28.
18. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, specified perfor-
mance is guaranteed only when using the ratios in Section 4.2.1 Master Mode on page 30 and Section
4.2.2 Slave Mode on page 30.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock (MCLKx = MCLK1, MCLK2)
MCLKx Frequency
MCLKx Duty Cycle
1.024
40
-
50
41.4720
60
MHz
%
Sample Rates
Single-Speed Mode
Double-Speed Mode
-
4
50
-
54
108
kHz
Master Mode
SCLKx Frequency
SCLKx Period
1/(128*108 kHz)
SCLKx Duty Cycle (Note 17)
-
tPERIOD
tHIGH ÷ tPERIOD
64•Fs
72.3
40
-
-
50
64•Fs
-
60
Hz
ns
%
LRCKx setup
before SCLK rising
LRCKx hold
after SCLK rising
tSETUP1
tHOLD1
20
20
--
ns
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising
tSETUP2
tHOLD2
10
10
--
ns
Slave Mode
SCLKx Frequency (Note 18)
SCLKx Period
1/(128•108 kHz)
SCLKx Duty Cycle
-
tPERIOD
tHIGH ÷ tPERIOD
-
72.3
40
64•Fs
-
50
-
-
60
Hz
ns
%
LRCKx setup
before SCLK rising
LRCKx hold
after SCLK rising
tSETUP1
tHOLD1
20
20
--
ns
SDOUT setup
before SCLK rising
SDOUT hold
after SCLK rising
tSETUP2
tHOLD2
10
10
--
ns
Figure 3. Serial Input Timing
LRCKx
SDOUT
SCLKx
data
channel
channel
data
tHOLD2
tSETUP2
tHOLD1
tSETUP1
tPERIOD
tHIGH



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