CS42324 datasheet(54/71 Pages) CIRRUS

54 / 71 page

DS721A6

CS42324

6.10.4

DAC1 Zero Cross Control

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-

out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel.

Soft Ramp and Zero Cross Enable

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-

ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel.

6.10.5

DAC1 Loop-Back

Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.

6.10.6

DAC1 Invert Signal Polarity

When enabled, this bit will effect a 180 degree phase shift in the DAC1 channels.

6.10.7

DAC1 Channel Mixer

These bits implement mono mixes of the left and right channels as well as a left/right channel swap.

DAC1_SOFT

DAC1_ZC

Mode

Changes to affect immediately

Zero Cross enabled

Soft Ramp enabled

Soft Ramp and Zero Cross enabled

DAC1_LOOP_

BACK

DAC1 Loop-Back

Off

DAC1_INV

DAC1 Invert Signal Polarity

Off

DAC1_MIX[1:0]

DAC1 OUTA

DAC1 OUTB

-----------

CS42324 数据表(PDF) 54 Page - Cirrus Logic

CS42324 数据表(HTML) 54 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

数据表下载