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CS42324 数据表(PDF) 25 Page - Cirrus Logic

部件名 CS42324
功能描述  10-In, 6-Out, 2 Vrms Audio CODEC
PDF  71 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS42324 数据表(HTML) 25 Page - Cirrus Logic

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DS721A6
25
CS42324
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT
Inputs: Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VLC; CL =20pF.
Notes: 20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For FSCK < 1 MHz.
23. CDOUT should not be sampled during this time.
Figure 6. Software Mode Timing - SPI Mode
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling (Note 20)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time (Note 21)
tdh
15
-
ns
Rise Time of CCLK and CDIN (Note 22)
tr2
-100
ns
Fall Time of CCLK and CDIN (Note 22)
tf2
-100
ns
Transition Time from CCLK to CDOUT Valid (Note 23)
tr2
-100
ns
Time from CS rising to CDOUT High-Z
tf2
-100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCLK
CDIN
t css
t csh
t spi
t srs
RST
CDOUT
t
scdov
t
scdov
t cscdo
Hi-Im pedance



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