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CS42324 数据表(PDF) 12 Page - Cirrus Logic |
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CS42324 数据表(HTML) 12 Page - Cirrus Logic |
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12 / 71 page ![]() 12 DS721A6 CS42324 1.3 Digital I/O Pin Characteristics The logic level for each input should adhere to the corresponding power rail and should not exceed the max- imum ratings. Power Supply Pin Number Pin Name I/O Driver Receiver Software Mode VL 1SDA CDOUT Input/Output Hi-Z/Output 1.8 V - 3.3 V, Open Drain 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V, with Hysteresis 2 SCL CCLK Input - 1.8 V - 3.3 V, with Hysteresis 3 AD0 CS Input - 1.8 V - 3.3 V, with Hysteresis 4 AD1 CDIN Input - 1.8 V - 3.3 V, with Hysteresis 5 INT Output 1.8 V - 3.3 V, Open Drain 1.8 V - 3.3 V, with Hysteresis Hardware Mode VL 1 M0 Input - 1.8 V - 3.3 V, with Hysteresis 2 M1 Input - 1.8 V - 3.3 V, with Hysteresis 3 MDIV Input - 1.8 V - 3.3 V, with Hysteresis 4 MUTE Input - 1.8 V - 3.3 V, with Hysteresis 5 DIF Input - 1.8 V - 3.3 V, with Hysteresis All Modes VL 35 RST Input - 1.8 V - 3.3 V 47 40 LRCK1 LRCK2 Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V 46 41 SCLK1 SCLK2 Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V 48 39 MCLK1 MCLK2 Input - 1.8 V - 3.3 V 38 37 SDIN1 SDIN2 Input - 1.8 V - 3.3 V 45 SDOUT Output 1.8 V - 3.3 V, CMOS - 36 OVFL Output 1.8 V - 3.3 V, Open Drain - VA_H 11 12 13 MUTEC1 MUTEC2 MUTEC3 Output 9.0 V - 12.0 V - Table 1. I/O Power Rails |
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