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数据搜索系统，热门电子元器件搜索 |
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ST7263BEx 数据表(PDF) 143 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 143 Page - STMicroelectronics |
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143 / 186 page  ST7263Bxx Electrical characteristics Doc ID 7516 Rev 8 143/186 Figure 56. Typ. IDD in Wait at fCPU= 4 and 8 MHz 13.5 Clock and timing characteristics Subject to general operating conditions for VDD, fCPU, and TA. Idd WFI (mA) at fcpu=4 and 8MHz 0 2 4 6 8 10 4 4.2 4.4 4.6 4.8 5 5.2 5.4 Vdd (V) 8MHz 4MHz ai15594 Table 61. General timings Symbol Parameter Conditions Min Typ(1) 1. Data based on typical application software. Max Unit tc(INST) Instruction cycle time fCPU=8 MHz 23 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time(2) tv(IT) = Δtc(INST) + 10 tCPU 2. Time measured between interrupt event and interrupt vector fetch. Δt c(INST) is the number of tCPU cycles needed to finish the current instruction execution. fCPU=8 MHz 10 - 22 tCPU 1.25 - 2.75 μs Table 62. Control timing characteristics Symbol Parameter Conditions Value Unit Min Typ. Max fOSC Oscillator frequency - - 24 MHz fCPU Operating frequency - - 8 MHz tRL External reset input pulse width 2520 - - ns tPORL Internal power reset duration 4096 - - tCPU tWDGL Watchdog or low voltage reset output pulse width 200 300 - ns |
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