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ST7263BEx 数据表(PDF) 144 Page - STMicroelectronics |
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ST7263BEx 数据表(HTML) 144 Page - STMicroelectronics |
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144 / 186 page ![]() Electrical characteristics ST7263Bxx 144/186 Doc ID 7516 Rev 8 Figure 57. Typical application with an external clock source tWDG Watchdog timeout fCPU = 8MHz 49152 - 3145728 tCPU 6.144 - 393.216 ms tOXOV Crystal oscillator startup time 20(1) 30 40(1) ms tDDR Power up rise time from VDD = 0 to 4 V - - 100(1) ms 1. Not tested in production, guaranteed by characterization. Table 62. Control timing characteristics Table 63. External clock source Symbol Parameter Conditions Min Typ Max Unit VOSCINH OSCIN input pin high level voltage see Figure 57 0.7xVDD -VDD V VOSCINL OSCIN input pin low level voltage VSS -0.3xVDD tw(OSCINH) tw(OSCINL) OSCIN high or low time(1) 15 - - ns tr(OSCIN) tf(OSCIN) OSCIN rise or fall time(1) -- 15 IL OSCx input leakage current VSS≤VIN≤VDD -- ±1 μA 1. Data based on design simulation and/or technology characteristics, not tested in production. OSCIN OSCOUT fOSC EXTERNAL ST72XXX CLOCK SOURCE Not connected internally VOSCINL VOSCINH tr(OSCIN) tf(OSCIN) tw(OSCINH) tw(OSCINL) IL 90% 10% |
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