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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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910GL 数据表(PDF) 185 Page - Intel Corporation |
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910GL 数据表(HTML) 185 Page - Intel Corporation |
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185 / 426 page  Integrated Graphics Device Registers (D2:F0) (Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only) R Datasheet 185 9.1.17 CAPPOINT—Capabilities Pointer (D2:F0) PCI Device: 2 Address Offset: 34h Default Value: D0h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO D0h Capabilities Pointer Value: This field contains an offset into the function’s PCI configuration space for the first item in the New Capabilities Linked List; the Power Management Capabilities ID registers at address D0h. 9.1.18 INTRLINE—Interrupt Line (D2:F0) PCI Device: 2 Address Offset: 3Ch Default Value: 00h Access: R/W Size: 8 bits Bit Access & Default Description 7:0 R/W 00h Interrupt Connection: This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller that the device’s interrupt pin is connected to. 9.1.19 INTRPIN—Interrupt Pin (D2:F0) PCI Device: 2 Address Offset: 3Dh Default Value: 01h Access: RO Size: 8 bits Bit Access & Default Description 7:0 RO 01h Interrupt Pin: As a device that only has interrupts associated with a single function, the IGD specifies INTA# as its interrupt pin. 01h = INTA#. |
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