910GL datasheet(182/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

182

Datasheet

9.1.12

GMADR—Graphics Memory Range Address (D2:F0)

PCI Device:

Address Offset:

18h

Default Value:

00000008h

Access:

RO, R/W/L

Size:

16 bits

IGD graphics memory base address is specified in this register.

Bit

Access &

Default

Description

31:28

R/W

Memory Base Address: Set by the OS, these bits correspond to address

signals [31:28].

R/W/L

256-MB Address Mask: This bit is either part of the Memory Base Address

(R/W) or part of the Address Mask (RO), depending on the value of MSAC[1].

See MSAC (Dev 2, Func 0, offset 62) for details.

26:4

000000h

Address Mask: Hardwired to 0s to indicate at least 128-MB address range

Prefetchable Memory: Hardwired to 1 to enable prefetching

2:1

00b

Memory Type: Hardwired to 0 to indicate 32-bit address.

Memory/IO Space: Hardwired to 0 to indicate memory space.

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