910GL datasheet(180/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

180

Datasheet

9.1.9

HDR2—Header Type (D2:F0)

PCI Device:

Address Offset:

0Eh

Default Value:

80h

Access:

Size:

8 bits

This register contains the Header Type of the IGD.

Bit

Access &

Default

Description

Multi Function Status (MFunc): This bit indicates if the device is a Multi-

Function Device. The Value of this register is determined by Device 0, offset 54h,

DEVEN[4]. If Device 0 DEVEN[4] is set, the Mfunc bit is also set.

6:0

00h

Header Code (H): This is a 7-bit value that indicates the Header Code for the

IGD. This code has the value 00h, indicating a type 0 configuration space format.

9.1.10

MMADR—Memory Mapped Range Address (D2:F0)

PCI Device:

Address Offset:

10h

Default Value:

00000000h

Access:

RO, R/W

Size:

32 bits

This register requests allocation for the IGD registers and instruction ports. The allocation is for

512 KB and the base address is defined by bits [31:19].

Bit

Access &

Default

Description

31:19

R/W

0000h

Memory Base Address: Set by the OS, these bits correspond to address

signals [31:19].

18:4

0000h

Address Mask: Hardwired to 0s to indicate 512 KB address range.

Prefetchable Memory: Hardwired to 0 to prevent prefetching.

2:1

00b

Memory Type: Hardwired to 0s to indicate 32-bit address.

Memory / IO Space: Hardwired to 0 to indicate memory space.

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