910GL datasheet(183/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

Datasheet

183

9.1.13

GTTADR—Graphics Translation Table Range Address

(D2:F0)

PCI Device:

Address Offset:

1Ch

Default Value:

00000000h

Access:

RO, R/W

Size:

32 bits

This register requests allocation for Graphics Translation Table Range. The allocation is for

256 KB and the base address is defined by bits [31:18].

Bit

Access &

Default

Description

31:18

R/W

0000h

Memory Base Address: Set by the OS, these bits correspond to address

signals [31:18].

17:4

0000h

Address Mask: Hardwired to 0s to indicate 256-KB address range.

Prefetchable Memory: Hardwired to 0 to prevent prefetching.

2:1

00b

Memory Type: Hardwired to 0s to indicate 32-bit address.

Memory/IO Space: Hardwired to 0 to indicate memory space.

9.1.14

SVID2—Subsystem Vendor Identification (D2:F0)

PCI Device:

Address Offset:

2Ch

Default Value:

0000h

Access:

R/WO

Size:

16 bits

Bit

Access &

Default

Description

15:0

R/WO

0000h

Subsystem Vendor ID. This value is used to identify the vendor of the

subsystem. This register should be programmed by BIOS during boot-up. Once

written, this register becomes Read-Only. This register can only be cleared by a

Reset.

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