910GL datasheet(179/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

Datasheet

179

9.1.7

CLS—Cache Line Size (D2:F0)

PCI Device:

Address Offset:

0Ch

Default Value:

00h

Access:

Size:

8 bits

The IGD does not support this register as a PCI slave.

Bit

Access &

Default

Description

7:0

00h

Cache Line Size (CLS): This field is hardwired to 0s. The IGD, as a PCI

compliant master, does not use the Memory Write and Invalidate command and,

in general, does not perform operations based on cache line size.

9.1.8

MLT2—Master Latency Timer (D2:F0)

PCI Device:

Address Offset:

0Dh

Default Value:

00h

Access:

Size:

8 bits

The IGD does not support the programmability of the master latency timer because it does not

perform bursts.

Bit

Access &

Default

Description

7:0

00h

Master Latency Timer Count Value: Hardwired to 0s.

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