ADP1046ACPZ-R7 datasheet(32/96 Pages) AD

32 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 32 of 96

VOLT-SECOND BALANCE

The ADP1046 has a dedicated circuit to maintain volt-second

balance in the main transformer when operating in full-bridge

topology. This circuit eliminates the need for a dc blocking capac-

itor. In interleaved topologies, volt-second balance can also be

used for current balancing to ensure that each interleaved phase

contributes equal power.

The circuit monitors the current flowing in both legs of the full-

bridge topology and stores this information. It compensates the

selected PWM signals to ensure equal current flow in both legs

of the full-bridge topology. The input is through the CS1 pin.

Several switching cycles are required for the circuit to operate

effectively. The maximum amount of modulation applied to

each edge of the selected PWM outputs is programmable to

±80 ns or ±160 ns in Register 0x28[2].

The volt-second balance settings are programmed in Register 0x28

and in Register 0x76 through Register 0x78. It is recommended

that the Analog Devices software GUI be used to program these

settings.

The compensation of the PWM drive signals is performed on

the edges of two selected outputs. The SR1 and SR2 edges can

also be independently set to modulate due to the volt-second

balance circuit to maintain the timing relation to the primary

side signals.

DIGITAL LOAD LINE AND SLEW RATE

The ADP1046 can optionally introduce a digital load line into

the power supply. This option is programmed in the load line

impedance register (Register 0x36). Two parameters can be

configured independently: slew rate and load line value.

The slew rate (Register 0x36[6:4]) determines how quickly the

output voltage is adjusted in response to a change in the digital

reference. Eight different settings are available.

The load line value (Register 0x36[2:0]) controls the slope of

the load line. The amount of output resistance introduced can

be calculated as follows:

ROUT = 0.1 × VOUT_NOM × CS2 RSENSE/(CS2 Range × 2LOAD_SET[2:0])

where:

VOUT_NOM is the nominal output voltage when VS3 = 1 V.

CS2 RSENSE is the sense resistor value.

CS2 Range is 120 mV or 60 mV.

LOAD_SET[2:0] is the value of Bits[2:0] in Register 0x36

(0 to 7 decimal).

For example, if VOUT_NOM = 12 V, CS2 RSENSE = 10 mΩ,

CS2 Range = 120 mV, and LOAD_SET[2:0] = 3,

ROUT = 0.1 × 12 V × 10 mΩ/(120 mV × 23) = 12.5 mΩ

This feature can be used for advanced current sharing techniques.

By default, the load line is disabled. The load line is introduced

digitally by modifying the value of the digital reference based

on the CS2 reading.

Figure 42 and Figure 43 show the load line as a percentage of

VOUT vs. the RSENSE voltage drop.

100

20406080

100

120

110

RSENSE VOLTAGE DROP (mV)

SETTING 7

SETTING 6

SETTING 5

SETTING 4

SETTING 3

SETTING 2

SETTING 1

SETTING 0

Figure 42. Load Line Settings with 120 mV CS2 Range

100

10203040

5060

253545

RSENSE VOLTAGE DROP (mV)

SETTING 7

SETTING 6

SETTING 5

SETTING 4

SETTING 3

SETTING 2

SETTING 1

SETTING 0

Figure 43. Load Line Settings with 60 mV CS2 Range

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