ADP1046ACPZ-R7 datasheet(56/96 Pages) AD

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ADP1046

Data Sheet

Rev. 0 | Page 56 of 96

Table 37. Register 0x25—CS2 Digital Offset Trim

Bits

Bit Name

R/W

Description

[7:0]

CS2 digital offset trim

R/W

This register contains the CS2 digital trim level. This value is used to calibrate the CS2 value

that is read in Register 0x18. See the CS2 Trim section for more information.

Table 38. Register 0x26—CS2 Accurate OCP Limit

Bits

Bit Name

R/W

Description

[7:0]

CS2 accurate OCP

R/W

This register sets the CS2 accurate OCP current level. This 8-bit number is compared to the CS2 value

the CS2 accurate OCP flag is set. The following equation gives the CS2 accurate OCP threshold:

CS2_OCP_Threshold = CS2_OCP_Limit × (ADC_Range)/256 + 16 × (ADC_Range)/212

Table 39. Register 0x27—CS1/CS2 Fast OCP Settings

Bits

Bit Name

R/W

Description

[7:6]

CS1 fast OCP debounce

R/W

These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal

must be constantly above the fast OCP limit before the PWM outputs are shut down. When this

happens, all PWM outputs are disabled for the remainder of the switching cycle.

Bit 7

Bit 6

Debounce (ns)

120

CS2 nominal voltage

drop

R/W

These bits set the nominal full-scale voltage drop across the sense resistor. See the CS2 Trim

section for more information. These bits set the LSB step size of the CS2 ADC.

Bit 5

ADC Range (mV)

LSB Step Size (μV)

14.65

120

29.30

CS1 fast OCP bypass

R/W

Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin.

Constant current mode

R/W

When this bit is set, constant current mode is enabled to 97% of the CS2 accurate OCP limit.

1 = constant current mode enabled.

0 = constant current mode disabled.

CS2 current sensing

R/W

This bit is set high if high-side current sensing is used. This bit is set low if low-side current

sensing is used. See the CS2 Trim section for more information.

[1:0]

CS1 fast OCP timeout

R/W

If the CS1 fast OCP comparator is set, all PWM outputs that are on at that time are immediately

disabled for the remainder of the switching cycle. The PWM outputs resume normal operation at

the beginning of the next switching cycle. These bits set the number of consecutive switching

cycles for the comparator before the CS1 fast OCP response is activated.

Bit 1

Bit 0

Number of Switching Cycles

188

440

Table 40. Register 0x28—Volt-Second Balance Settings

Bits

Bit Name

R/W

Description

Reserved

R/W

Reserved.

Volt-second balance

enable

R/W

Setting this bit enables volt-second balance for the main transformer (used for full-bridge

configurations). For more information, see the Volt-Second Balance section.

Volt-second balance

leading edge blanking

R/W

Setting this bit means that CS1 is blanked for volt-second balance calculations at the rising

edge of the PWM outputs that are selected for volt-second balance. The blanking value is the

same value configured for CS1 fast OCP blanking in Register 0x22[7:5].

Volt-second disable

during soft start

R/W

0 = do not blank volt-second balance control during soft start.

1 = blank volt-second balance control during soft start.

50% blanking of each

phase

R/W

Setting this bit limits the sampling period for the current on CS1 to less than 50% of a half cycle.

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