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ADP1046ACPZ-R7 数据表(PDF) 83 Page - Analog Devices |
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ADP1046ACPZ-R7 数据表(HTML) 83 Page - Analog Devices |
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83 / 96 page  Data Sheet ADP1046 Rev. 0 | Page 83 of 96 Table 124. Register 0x7C—PGOOD2 Flag Masking Bits Bit Name R/W Description 7 Soft start flag R/W If set to 1, this flag is ignored by PGOOD2. This bit must be set to 0 to enable proper PGOOD2 debounce timing after the end of the soft start ramp. 6 CS1 fast OCP R/W If set to 1, this flag is ignored by PGOOD2. 5 CS1 accurate OCP R/W If set to 1, this flag is ignored by PGOOD2. 4 CS2 accurate OCP R/W If set to 1, this flag is ignored by PGOOD2. 3 UVP R/W If set to 1, this flag is ignored by PGOOD2. 2 Local OVP (fast and accurate) R/W If set to 1, this flag is ignored by PGOOD2. 1 Load OVP R/W If set to 1, this flag is ignored by PGOOD2. 0 OrFET R/W If set to 1, this flag is ignored by PGOOD2. Table 125. Register 0x7D—Light Load Mode Threshold Settings Bits Bit Name R/W Description [7:6] Reserved R/W Reserved. [5:4] Debounce R/W After the SR outputs are turned on or off, any further transition of the thresholds is ignored for the amount of time programmed in these bits. This debounce is provided to avoid false transitions and improve noise immunity. The debounce time is calculated as a number of PWM switching cycles (tSW). For example, at 100 kHz, tSW = 10 μs, 64 × tSW = 640 μs. Bit 5 Bit 4 Debounce Time 0 0 0 tSW 0 1 64 tSW 1 0 128 tSW 1 1 256 tSW [3:2] Light load mode averaging speed R/W These bits set the averaging speed and resolution used for the light load mode threshold. Faster speed corresponds to lower resolution and, therefore, to lower accuracy of the threshold. Bit 3 Bit 2 Speed (Resolution) 0 0 37.5 μs (6 bits) 0 1 75 μs (7 bits) 1 0 150 μs (8 bits) 1 1 300 μs (9 bits) [1:0] Light load mode hysteresis R/W These bits set the amount of hysteresis applied to the light load mode threshold. The size of the LSB is affected by the speed and resolution selected in Bits[3:2]. If the CS2 ADC range of 120 mV is used with 8-bit resolution, the LSB size is 120 mV/28 = 469 μV. Bit 1 Bit 0 Hysteresis (LSB) 0 0 3 0 1 8 1 0 12 1 1 16 Table 126. Register 0x7F—GO Byte Bits Bit Name R/W Description [7:4] Reserved R/W Reserved. 3 Filter GO W This bit latches all the filter registers: Register 0x60 to Register 0x67 and Register 0x71 to Register 0x75. 2 Frequency GO W This bit latches Register 0x3F and Register 0x40. This is to prevent the switching frequency settings from being temporarily incorrect. 1 PWM settings GO W This bit latches Register 0x41 to Register 0x5C. This is to prevent the PWM settings from being temporarily incorrect. 0 Voltage reference GO W This bit latches Register 0x31. This is to prevent the reference setting from being temporarily incorrect. |
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