 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADP1046ACPZ-R7 数据表(PDF) 75 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADP1046ACPZ-R7 数据表(HTML) 75 Page - Analog Devices |
|
|
75 / 96 page  Data Sheet ADP1046 Rev. 0 | Page 75 of 96 Bits Bit Name R/W Description [2:0] Slew rate R/W These bits specify the slew rate at the VS3± pins for the change in the voltage reference setting. Bit 2 Bit 1 Bit 0 Slew Rate 0 0 0 200 mV/ms 0 0 1 100 mV/ms 0 1 0 50 mV/ms 0 1 1 25 mV/ms 1 0 0 12.5 mV/ms 1 0 1 6.25 mV/ms 1 1 0 3.125 mV/ms 1 1 1 1.5625 mV/ms (4 LSB/ms) Table 96. Register 0x60—Normal Mode Digital Filter LF Gain Setting Bits Bit Name R/W Description [7:0] LF gain setting R/W This register determines the low frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 97. Register 0x61—Normal Mode Digital Filter Zero Setting Bits Bit Name R/W Description [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 98. Register 0x62—Normal Mode Digital Filter Pole Setting Bits Bit Name R/W Description [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 99. Register 0x63—Normal Mode Digital Filter HF Gain Setting Bits Bit Name R/W Description [7:0] HF gain setting R/W This register determines the high frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 100. Register 0x64—Light Load Mode Digital Filter LF Gain Setting Bits Bit Name R/W Description [7:0] LF gain setting R/W This register determines the low frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. Table 101. Register 0x65—Light Load Mode Digital Filter Zero Setting Bits Bit Name R/W Description [7:0] Zero setting R/W This register determines the position of the final zero. See Figure 57. Table 102. Register 0x66—Light Load Mode Digital Filter Pole Setting Bits Bit Name R/W Description [7:0] Pole location R/W This register determines the position of the final pole. See Figure 57. Table 103. Register 0x67—Light Load Mode Digital Filter HF Gain Setting Bits Bit Name R/W Description [7:0] HF gain setting R/W This register determines the high frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 57. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
