ADP1046ACPZ-R7 datasheet(82/96 Pages) AD

82 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 82 of 96

Table 120. Register 0x78—Volt-Second Balance Settings (SR1 and SR2 Pins)

Bits

Bit Name

R/W

Description

Modulate enable, t9

R/W

Setting this bit enables modulation from balance control on the SR1 rising edge, t9.

t9 sign

R/W

0 = positive sign. Increase of balance control modulation moves t9 right.

1 = negative sign. Increase of balance control modulation moves t9 left.

Modulate enable, t10

R/W

Setting this bit enables modulation from balance control on the SR1 falling edge, t10.

t10 sign

R/W

0 = positive sign. Increase of balance control modulation moves t10 right.

1 = negative sign. Increase of balance control modulation moves t10 left.

Modulate enable, t11

R/W

Setting this bit enables modulation from balance control on the SR2 rising edge, t11.

t11 sign

R/W

0 = positive sign. Increase of balance control modulation moves t11 right.

1 = negative sign. Increase of balance control modulation moves t11 left.

Modulate enable, t12

R/W

Setting this bit enables modulation from balance control on the SR2 falling edge, t12.

t12 sign

R/W

0 = positive sign. Increase of balance control modulation moves t12 right.

1 = negative sign. Increase of balance control modulation moves t12 left.

Table 121. Register 0x79—SR Delay Compensation

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

[5:0]

SR driver delay

R/W

These bits specify the 6-bit representation of the SR delay in steps of 5 ns.

000000 = 0 ns.

111111 = 63 ns × 5 ns = 315 ns.

Table 122. Register 0x7A—Filter Transitions

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

[5:3]

HF ADC configuration

R/W

Set these bits to 001 at all times for proper operation.

Enable soft transition

R/W

Setting this bit enables a soft transition between filter settings to minimize output transients.

All four parameters of each filter are linearly transitioned to the new value.

[1:0]

Transition speed

R/W

These bits set the transition speed from one filter to another. The filter changes in 32 steps;

each step is applied at the multiple of switching cycles (tSW) specified by these bits.

Bit 1

Bit 0

Speed (tSW = One Switching Cycle)

32 tSW (total transition time = 32 × 32 tSW = 1024 × tSW)

8 tSW (total transition time = 8 × 32 tSW = 256 × tSW)

2 tSW (total transition time = 64 × tSW)

1 tSW (total transition time = 32 × tSW)

Table 123. Register 0x7B—PGOOD1 Flag Masking

Bits

Bit Name

R/W

Description

Soft start flag

R/W

If set to 1, this flag is ignored by PGOOD1. This bit must be set to 0 to enable proper PGOOD1

debounce timing after the end of the soft start ramp.

CS1 fast OCP

R/W