ADP1046ACPZ-R7 datasheet(58/96 Pages) AD

58 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 58 of 96

Bits

Bit Name

R/W

Description

Reserved

R/W

Set this bit to zero for normal operation.

Disable light load

during soft start

R/W

0 = allow switching to light load mode filter during soft start.

1 = never switch to light load mode filter during soft start.

Force soft start

filter

R/W

0 = use normal mode filter or soft start filter, depending on the OrFET status. If regulating from

VS3 (OrFET on), the normal mode filter is used. If regulating from VS1 (OrFET off ), the soft start

filter is used.

1 = use soft start filter as the initial filter regardless of OrFET status.

Table 45. Register 0x2D—PGOOD Debounce and Pin Polarity Settings

Bits

Bit Name

R/W

Description

[7:6]

PGOOD1 turn-on

debounce

R/W

These bits set the debounce time before the PGOOD1 pin and flag are set. This debounce time

starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD1 is always

immediate (no debounce).

Bit 7

Bit 6

Typical Debounce Time (ms)

350

150

550

[5:4]

PGOOD2 turn-on

debounce

R/W

These bits set the debounce time before the PGOOD2 pin and flag are set. This debounce time

starts at the end of the soft start ramp and can vary by ±50 ms. The turn-off of PGOOD2 is always

immediate (no debounce).

Bit 5

Bit 4

Typical Delay Time (ms)

350

150

550

PGOOD2 flags

R/W

The following flags can also set the PGOOD2 pin: voltage continuity, OrFET disable, ACSNS, FLAGIN,

and OTP. This bit specifies whether these flags unconditionally set PGOOD2 or whether these flags

set PGOOD2 only if the flag action is not set to ignore (Bits[6:4] = 000) in the appropriate fault

configuration register (see Table 12 and Table 13).

0 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags always set the PGOOD2 pin.

1 = voltage continuity, OrFET disable, ACSNS, FLAGIN, and OTP flags set the PGOOD2 pin only if the

flag action is not set to “ignore.”

FLAGIN polarity

R/W

This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = 0 V = on).

GATE polarity

R/W

This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = 0 V = on).

PSON polarity

R/W

This bit sets the polarity of the PSON input pin: 1 = inverted (low = 0 V = on).

Table 46. Register 0x2E—Modulation Limit

Bits

Bit Name

R/W

Description

Full-bridge mode

R/W

Enable this bit when operating in full-bridge mode. It affects the modulation high limit.

[6:0]

Modulation limits

R/W

This value sets the minimum/maximum modulation limits relative to the nominal edge value. The

resolution depends on the switching frequency range.

Switching Frequency Range

Resolution Corresponding to LSB

48.8 kHz to 86.8 kHz

160 ns

97.7 kHz to 183.8 kHz

80 ns

195 kHz to 378.8 kHz

40 ns

390.6 kHz to 625.0 kHz

20 ns

ADP1046ACPZ-R7 数据表(PDF) 58 Page - Analog Devices

ADP1046ACPZ-R7 数据表(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载

链接网址

ADP1046ACPZ-R7 数据表(PDF) 58 Page - Analog Devices

ADP1046ACPZ-R7 数据表(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表 下载

链接网址

数据表下载