ADP1046ACPZ-R7 datasheet(51/96 Pages) AD

51 / 96 page

Data Sheet

ADP1046

Rev. 0 | Page 51 of 96

Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions

Bits

Bit Name

R/W

Description

Timing

R/W

This bit specifies when the flag is set.

0 = after debounce.

1 = immediately.

[6:4]

Action

R/W

These bits specify the action that the part takes in response to the flag.

Bit 6

Bit 5

Bit 4

Action

Ignore flag completely

Disable SR1 and SR2

Disable OrFET

Disable the power supply and reenable it after the power

supply reenable time set in Register 0x0E[1:0]

Disable OUTAUX

Disable all PWM outputs except OUTAUX

Disable SR1, SR2, and OrFET

Disable the power supply and keep it disabled; PSON

signal is necessary to restart

Timing

R/W

Same as Bit 7.

[2:0]

Action

R/W

Same as Bits[6:4].

Table 14. Register 0x0E—Flag Configuration Register

Bits

Bit Name

R/W

Description

VDD OV/VCORE OV

flags ignore

R/W

Setting this bit to 1 means that the VDD OV and VCORE OV flags are ignored.

VDD OV/VCORE OV

restart

R/W

This bit specifies whether the part downloads the EEPROM contents before it restarts.

1 = if the part shuts down, it downloads the EEPROM contents again before restarting.

0 = if the part shuts down, it does not download the EEPROM contents again before restarting.

VDD OV/VCORE OV

debounce

R/W

Setting this bit to 1 means that there is a 500 μs debounce before the part shuts down. Setting

this bit to 0 means that there is a 2 μs debounce before the part shuts down.

[4:2]

Accurate OCP debounce

for CS1 and CS2

R/W

When an accurate OCP flag is set, there is a debounce time before the flag action is performed.

These bits set the flag debounce time. The ADC sampling rate adds a variable latency from

2.62 ms to 5.24 ms to this debounce time.

Bit 4

Bit 3

Bit 2

Debounce

2.6 ms

9.8 ms

130 ms

260 ms

600 ms

1.3 sec

2 sec

2.6 sec

[1:0]

Power supply reenable

time

R/W

These bits specify the time delay before restarting the power supply after a shutdown.

SR1, SR2, and OrFET are reenabled immediately.

Bit 1

Bit 0

Time (sec)

0.5

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