ADP1046ACPZ-R7 datasheet(90/96 Pages) AD

90 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 90 of 96

Table 158. Register 0x45—OUTB Rising Edge Dead Time in Resonant Mode

Bits

Bit Name

R/W

Description

[7:0]

Δt3 (rising edge dead

time of OUTB)

R/W

This register sets Δt3, which is the delay time of the rising edge of OUTB from the start of the

switching cycle, tA. Each LSB corresponds to 5 ns of resolution.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Δt3 (ns)

…

1275

Table 159. Register 0x46—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)

Bits

Bit Name

R/W

Description

[7:0]

Highest frequency

R/W

This register contains the eight MSBs of the 12-bit value of the highest switching frequency (mini-

mum switching cycle) limit. This value is always used with the top four bits of Register 0x48,

which contain the four LSBs of the highest switching frequency limit. Each LSB of the 12-bit

value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46

is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum

switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is

1/1.325 μs = 755 kHz. It is recommended that the maximum frequency be limited 1 MHz.

Table 160. Register 0x47—OUTB Falling Edge Dead Time in Resonant Mode

Bits

Bit Name

R/W

Description

[7:0]

Δt4 (falling edge dead

time of OUTB)

R/W

This register sets Δt4, which is the difference between the falling edge of OUTB and the mid-

point of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register

value is from 0x00 to 0x7F, the falling edge of OUTB is trailing tB. When the value is from 0x80

to 0xFF, the falling edge of OUTB is leading tB.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Δt4

0 ns

5 ns trailing

…

635 ns trailing

640 ns leading

…

5 ns leading

Table 161. Register 0x48—Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)

Bits

Bit Name

R/W

Description

[7:4]

Highest frequency

R/W

This register contains the four LSBs of the 12-bit value of the highest switching frequency (mini-

mum switching cycle) limit. This value is always used with the eight bits of Register 0x46, which

contain the eight MSBs of the highest switching frequency limit. Each LSB of the 12-bit value

corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to

0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum

switching cycle is (16 × 16 + 9) × 5 ns = 1.325 μs, and the highest switching frequency limit is

1/1.325 μs = 755 kHz.

[3:0]

Reserved

R/W

Reserved.

ADP1046ACPZ-R7 数据表(PDF) 90 Page - Analog Devices

ADP1046ACPZ-R7 数据表(HTML) 90 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表下载

链接网址

ADP1046ACPZ-R7 数据表(PDF) 90 Page - Analog Devices

ADP1046ACPZ-R7 数据表(HTML) 90 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

数据表 下载

链接网址

数据表下载