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ADP1046ACPZ-R7 数据表(PDF) 49 Page - Analog Devices |
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ADP1046ACPZ-R7 数据表(HTML) 49 Page - Analog Devices |
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49 / 96 page  Data Sheet ADP1046 Rev. 0 | Page 49 of 96 DETAILED REGISTER DESCRIPTIONS FAULT REGISTERS Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also note that these register bits are cleared when read via the I2C interface unless the fault is still present. It is recommended that the latched fault register be read again after the faults disappear to ensure that the register is reset. Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation) Bits Bit Name R/W Description Register Action 7 Power supply R 1 = power supply is off. All PWM outputs are disabled. This bit stays high until the power supply is restarted. None 6 OrFET R 1 = OrFET control signal at the GATE pin (Pin 16) is off. 0x30 5 PGOOD1 fault R 1 = Power-Good 1 fault. At least one of the following flags has been set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, load OVP, or OrFET (GATE). These flags can be masked using Register 0x7B. 0x2D None 4 PGOOD2 fault R 1 = Power-Good 2 fault. At least one of the following flags has been set: soft start flag, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, load OVP, or OrFET (GATE pin). These flags can be masked using Register 0x7C. The following flags can also set PGOOD2, either unconditionally or based on the flag response, as defined in Register 0x2D[3] (see Table 45): voltage continuity, OrFET disable, ACSNS, external flag (FLAGIN pin), and OTP. 0x2D None 3 SR off R SR1 and SR2 synchronous rectifiers are disabled. This flag is set when one of the following cases is true: None SR1 and SR2 are disabled by the user. 0x5D The load current has fallen below the threshold in Register 0x3B. 0x3B A flag has been set that is configured to disable the synchronous rectifiers. 0x08 to 0x0D 2 CS1 fast OCP R CS1 current is above its fast overcurrent protection limit. There is a 1.2 V threshold on the CS1 pin. Fast OCP is a comparator. Programmable 1 CS1 accurate OCP R CS1 current is above its accurate overcurrent protection limit. 0x22 Programmable 0 CS2 accurate OCP R CS2 current is above its accurate overcurrent protection limit. 0x26 Programmable Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation) Bits Bit Name R/W Description Register Action 7 Voltage continuity R Voltage differential between VS1 and VS2 pins or between VS2 and VS3± pins is outside limits. Either (VS1 − VS2) > 50 mV or (VS2 − VS3) > 50 mV at the pins. Programmable 6 UVP R VS1 is below its undervoltage limit. 0x34 Programmable 5 CS2 reverse current R Reverse voltage across the CS2± pins is above limit. This is the OrFET reverse voltage. 0x30 Programmable 4 VDD UV R VDD is below limit. Immediate shutdown 3 VCORE OV R 2.5 V VCORE is above limit. Immediate shutdown 2 VDD OV R VDD is above limit. The I2C interface stays functional, but a PSON toggle is required to restart the power supply. 0x0E Programmable 1 Load OVP R VS2 or VS3± is above its overvoltage limit. 0x33 Programmable 0 Local OVP R VS1 is above its overvoltage limit. 0x32 Programmable |
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