ADP1046ACPZ-R7 datasheet(72/96 Pages) AD

72 / 96 page

ADP1046

Data Sheet

Rev. 0 | Page 72 of 96

Table 86. Register 0x56—SR2 Rising Edge Setting (SR2 Pin)

Bits

Bit Name

R/W

Description

[7:4]

t11

R/W

These bits contain the four LSBs of the 12-bit t11 time. This value is always used with the eight

bits of Register 0x55, which contains the eight MSBs of the t11 time. Each LSB corresponds to 5 ns

resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of a

PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall

occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute

maximum pulse width is tPERIOD − 5 ns. It is recommended that the SR2 rising edge not be set

between 80 ns and 115 ns when using the SR soft start.

Modulate enable

R/W

1 = PWM modulation acts on the t11 edge.

0 = no PWM modulation of the t11 edge.

t11 sign

R/W

1 = negative sign. Increase of PWM modulation moves t11 right.

0 = positive sign. Increase of PWM modulation moves t11 left.

[1:0]

Reserved

R/W

Reserved.

Table 87. Register 0x57—SR2 Falling Edge Timing (SR2 Pin)

Bits

Bit Name

R/W

Description

[7:0]

t12

R/W

This register contains the eight MSBs of the 12-bit t12 time. This value is always used with the top

four bits of Register 0x58, which contains the four LSBs of the t12 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall

of a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and

t_fall occur in different 40 ns time steps, the PWM output is set to the programmed value. The

absolute maximum pulse width is tPERIOD − 5 ns.

Table 88. Register 0x58—SR2 Falling Edge Setting (SR2 Pin)

Bits

Bit Name

R/W

Description

[7:4]

t12

R/W

These bits contain the four LSBs of the 12-bit t12 time. This value is always used with the eight

bits of Register 0x57, which contains the eight MSBs of the t12 time. Each LSB corresponds to 5 ns

resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of a

PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall

occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute

maximum pulse width is tPERIOD − 5 ns.

Modulate enable

R/W

1 = PWM modulation acts on the t12 edge.

0 = no PWM modulation of the t12 edge.

t12 sign

R/W

1 = negative sign. Increase of PWM modulation moves t12 right.

0 = positive sign. Increase of PWM modulation moves t12 left.

[1:0]

Reserved

R/W

Reserved.

Table 89. Register 0x59—OUTAUX Rising Edge Timing (OUTAUX Pin)

Bits

Bit Name

R/W

Description

[7:0]

t13

R/W

This register contains the eight MSBs of the 12-bit t13 time. This value is always used with the top

four bits of Register 0x5A, which contains the four LSBs of the t13 time. Each LSB corresponds to

5 ns resolution. The entire switching period is divided into 40 ns time steps. If the t_rise and t_fall of

a PWM edge occur within the same 40 ns time step, the PWM output is 0 V. If the t_rise and t_fall

occur in different 40 ns time steps, the PWM output is set to the programmed value. The absolute

maximum pulse width is tPERIOD − 5 ns. Depending on the switching frequency and the OUTAUX

frequency, there is a constant lag/lead time between this edge and the other edges (t1 to t12); there-

fore, OUTAUX is not synchronized to the other PWM outputs but can be made synchronous by

adjusting the delay accordingly. If either the OUTAUX switching frequency (Register 0x3F) or the

PWM switching frequency (Register 0x40) is changed after edge adjustment, the synchronization

between OUTAUX and the PWM edges is no longer maintained. The OUTAUX delay must be adjusted

again to synchronize the edges to the PWM edges for the new set of switching frequencies.

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